Hi：
I am a Gem5 user and currently working on system-level modeling and simulation
using Gem5. I have encountered an issue and would greatly appreciate your
assistance and advice.
Currently, I am using tlm_slave.py to connect with TLM memory
successfully. However, I noticed that when using tlm_slave.py, it requires
pairing with the _TrafficGen CPU which is not a conventional CPU model;
instead, it is a special module used for generating memory system stimuli. I
would like to use the traditional processor simulator RiscvTimingSimpleCPU
instead of the _TrafficGen CPU to conduct more realistic instruction-level
simulation.
I am not familiar with the method of connecting RiscvTimingSimpleCPU with TLM
memory and would like to inquire whether it is possible to achieve this
configuration and what specific steps need to be taken.
During the configuration process, would I need to modify the interface of
RiscvTimingSimpleCPU or perform other customizations? Is the workload
significant?
Thank you very much for your help and guidance!
Best regards,
Zitai
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