[gem5-users] 回复：Re: Gem5 SE mode with SystemC for RISC-V

[泰。 via gem5-users]

Hi Harshil,


Thank you for providing the examples.



I tried util/tlm/conf/tlm_slave.py and it works. However, if I directly replace 
TrafficGen with TimingSimpleCPU, simulation doesn't work. 


Is there a better way to pass transactions to the TLM memory slave when using 
TimingSimpleCPU as the CPU?Or is this approach feasible?



Regards,
Zitai






Hi Zitai,

Here are  some examples of using SystemC with gem5:
https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.pyhttps://github.com/gem5/gem5/tree/develop/util/tlm



However, it should be noted that the integration of SystemC with gem5 is not 
being actively maintained by the community.



Regards,
Harshil
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