Strange thing I noticed on an m5.fast run of galgel: the CPU clock specified in the configuration py file is 2GHz but the clock that appears in config.ini is 500. I've attached the three files: galgel.p, the config.ini that was generated, and the final m5stats.txt. The command line was similar to 'm5.fast galgel.py'. Stranger still was the sim_freq from m5stats.txt, which was 1000000000000 (which matches sim_ticks/sim_seconds from the same output). Which is lying and which is telling the truth? And why didn't the 2GHz CPU clock get set? The other files referenced in the config files are unmodified from the m5 2.0b5 distro. |
config.ini
Description: Binary data
# Galgel script based on se.py
#
#
import m5
from m5.objects import *
import os, optparse, sys
m5.AddToPath('../../m5/configs/common')
import Simulation
from Caches import *
from cpu2000 import *
# Get paths we might need. It's expected this file is in m5/configs/example.
# config_path = os.path.dirname(os.path.abspath(__file__))
config_path = '../m5/configs/'
config_root = os.path.dirname(config_path)
m5_root = os.path.dirname(config_root)
parser = optparse.OptionParser()
# Benchmark options
parser.add_option("-c", "--cmd",
default=os.path.join(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
help="The options to pass to the binary, use \" \" around the entire\
string.")
parser.add_option("-i", "--input", default="",
help="A file of input to give to the binary.")
parser.add_option("--bench", action="store", type="string", default=None,
help="base names for --take-checkpoint and --checkpoint-restore")
parser.add_option("-S", "--simpoint", action="store_true", default=False,
help="""Use workload simpoints as an instruction offset for
--checkpoint-restore or --take-checkpoint.""")
execfile(os.path.join(config_root, "common", "Options.py"))
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
if options.bench:
try:
if m5.build_env['TARGET_ISA'] != 'alpha':
print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
sys.exit(1)
exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
process = workload.makeLiveProcess()
except:
print >>sys.stderr, "Unable to find workload for %s" % options.bench
sys.exit(1)
else:
process = LiveProcess()
process.executable = options.cmd
process.cmd = [options.cmd] + options.options.split()
if options.input != "":
process.input = options.input
if options.detailed:
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
process = []
smt_idx = 0
inputs = []
if options.input != "":
inputs = options.input.split(';')
for wrkld in workloads:
smt_process = LiveProcess()
smt_process.executable = wrkld
smt_process.cmd = wrkld + " " + options.options
if inputs and inputs[smt_idx]:
smt_process.input = inputs[smt_idx]
process += [smt_process, ]
smt_idx += 1
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = '2GHz'
np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = PhysicalMemory(range=AddrRange("512MB")),
membus = Bus(), mem_mode = test_mem_mode)
system.physmem.port = system.membus.port
if options.l2cache:
system.l2 = L2Cache(size='2MB')
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
for i in xrange(np):
if options.caches:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
if options.l2cache:
system.cpu[i].connectMemPorts(system.tol2bus)
else:
system.cpu[i].connectMemPorts(system.membus)
system.cpu[i].workload = process
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
root = Root(system = system)
Simulation.run(options, root, system, FutureClass)
---------- Begin Simulation Statistics ---------- host_inst_rate 2152602 # Simulator instruction rate (inst/s) host_mem_usage 631892 # Number of bytes of host memory used host_seconds 190167.52 # Real time elapsed on the host host_tick_rate 1123990605 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 409354922667 # Number of instructions simulated sim_seconds 213.746503 # Number of seconds simulated sim_ticks 213746503419500 # Number of ticks simulated system.cpu.dtb.accesses 137172878221 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations system.cpu.dtb.hits 119034794230 # DTB hits system.cpu.dtb.misses 18138083991 # DTB misses system.cpu.dtb.read_accesses 103927011511 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 88941391227 # DTB read hits system.cpu.dtb.read_misses 14985620284 # DTB read misses system.cpu.dtb.write_accesses 33245866710 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 30093403003 # DTB write hits system.cpu.dtb.write_misses 3152463707 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.itb.accesses 427493006840 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 427493006658 # ITB hits system.cpu.itb.misses 182 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 427493006840 # number of cpu cycles simulated system.cpu.num_insts 409354922667 # Number of instructions executed system.cpu.num_refs 197135657211 # Number of memory references system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ----------
Thanks, Dan
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