# Speck2K Run Script
#

import m5
from m5.objects import *
import os, optparse, sys
m5.AddToPath('../common')
from cpu2000 import *
import Simulation
from Caches import *

# --------------------
# Define Command Line Options
# ====================
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
m5_root = os.path.dirname(config_root)

parser = optparse.OptionParser()

parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-m", "--maxtick", type="int")
parser.add_option("-n", "--numcpus",default="1",
                  help="Number of cpus in total", type="int")
parser.add_option("-f", "--frequency",
                  default = "1GHz",
                  help="Frequency of each CPU")
#parser.add_option("-p", "--protocol",
#                  default="moesi",
#                  help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")
parser.add_option("--l1size",
                  default = "32kB")
parser.add_option("--l1latency",
                  default = '1ns')
parser.add_option("--l2size",
                  default = "256kB")
parser.add_option("--l2latency",
                  default = '10ns')
parser.add_option("--benchmarkdir",
                  help="(Relative) Directory of Spec2K Benchmarks",
                  default="/n/poolfs/dist/m5/cpu2000/")
parser.add_option("-b", "--benchmark",
                  help="Splash 2 benchmark to run")
parser.add_option("-k", "--num_banks", default="4")

workdir = m5_root + '/'

#execfile(os.path.join(config_root, "common", "Options.py"))

(options, args) = parser.parse_args()

if args:
    print "Error: script doesn't take any positional arguments"
    sys.exit(1)

process = LiveProcess()
    
# --------------------
# Define Spec2K Benchmarks
# ====================

# --------------------
# Base L1 Cache Definition
# ====================

class L1(BaseCache):
    latency = options.l1latency
    block_size = 64
    mshrs = 12
    tgts_per_mshr = 8

# ----------------------
# Base L2 Cache Definition
# ----------------------

class L2(BaseCache):
    block_size = 64
    latency = options.l2latency
    mshrs = 92
    tgts_per_mshr = 16
    write_buffers = 8

# ----------------------
# Define the cpus
# ----------------------

busFrequency = Frequency(options.frequency)

if options.timing:
    cpus = [TimingSimpleCPU(cpu_id = i,
                            clock=options.frequency)
            for i in xrange(options.numcpus)]
elif options.detailed:
    cpus = [DerivO3CPU(cpu_id = i,
                       clock=options.frequency)
            for i in xrange(options.numcpus)]
else:
    cpus = [AtomicSimpleCPU(cpu_id = i,
                            clock=options.frequency)
            for i in xrange(options.numcpus)]

# ----------------------
# Create a system, and add system wide objects
# ----------------------        
system = System(cpu = cpus, physmem = DRAMMemory(num_banks=options.num_banks, num_cpus=options.numcpus),
                membus = Bus(clock = busFrequency))

system.toL2bus = Bus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)

# ----------------------
# Connect the L2 cache and memory together
# ----------------------

system.physmem.port = system.membus.port
system.l2.cpu_side = system.toL2bus.port
system.l2.mem_side = system.membus.port

# ----------------------
# Connect the L2 cache and clusters together
# ----------------------
for cpu in cpus:
    cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
                                L1(size = options.l1size, assoc = 4))
    cpu.mem = cpu.dcache
    # connect cpu level-1 caches to shared level-2 cache
    cpu.connectMemPorts(system.toL2bus)




# --------------------
# Pick the correct Spec2K Benchmarks
# ====================

if options.benchmark == 'gzip':
    process = gzip_log('alpha', 'linux', 'smred')

else:
    panic("The --benchmark environment variable was set to something" \
          +" improper.\nUse gzip\n")

# --------------------
# Assign the workload to the cpus
# ====================

for cpu in cpus:
    system.cpu.workload = process.makeLiveProcess()

# ----------------------
# Define the root
# ----------------------

root = Root(system = system)

# ----------------------
# Run the simulation
# ----------------------

if options.timing or options.detailed:
    root.system.mem_mode = 'timing'

# instantiate configuration
m5.instantiate(root)

# simulate until program terminates
if options.maxtick:
    exit_event = m5.simulate(options.maxtick)
else:
    exit_event = m5.simulate(m5.MaxTick)

print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()