I just used m5 latest beta. I run a simple script with 8 cores and radix
benchmark (multiple threads). When I use the --trace-flags="Bus,Cache" option,
it gives statistics and (possibly) run only one cpu. Attached is the script.
# Simple test script
#
# "m5 test.py"
import m5
from m5.objects import *
import os, optparse, sys
m5.AddToPath('../common')
import Simulation
from Caches import *
from cpu2000 import *
# Get paths we might need. It's expected this file is in m5/configs/example.
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
m5_root = os.path.dirname(config_root)
parser = optparse.OptionParser()
# Benchmark options
parser.add_option("-c", "--cmd",
default=os.path.join(m5_root,
"tests/test-progs/radix/bin/radix"),
help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
help="The options to pass to the binary, use \" \" around the
entire\
string.")
parser.add_option("-i", "--input", default="",
help="A file of input to give to the binary.")
parser.add_option("--bench", action="store", type="string", default=None,
help="base names for --take-checkpoint and
--checkpoint-restore")
parser.add_option("-S", "--simpoint", action="store_true", default=False,
help="""Use workload simpoints as an instruction offset for
--checkpoint-restore or --take-checkpoint.""")
execfile(os.path.join(config_root, "common", "Options.py"))
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
if options.bench:
try:
if m5.build_env['TARGET_ISA'] != 'alpha':
print >>sys.stderr, "Simpoints code only works for Alpha ISA at
this time"
sys.exit(1)
exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
process = workload.makeLiveProcess()
except:
print >>sys.stderr, "Unable to find workload for %s" % options.bench
sys.exit(1)
else:
process = LiveProcess()
process.executable = options.cmd
process.cmd = [options.cmd] + options.options.split()
if options.input != "":
process.input = options.input
if options.detailed:
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
process = []
smt_idx = 0
inputs = []
if options.input != "":
inputs = options.input.split(';')
for wrkld in workloads:
smt_process = LiveProcess()
smt_process.executable = wrkld
smt_process.cmd = wrkld + " " + options.options
if inputs and inputs[smt_idx]:
smt_process.input = inputs[smt_idx]
process += [smt_process, ]
smt_idx += 1
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = '2GHz'
options.num_cpus = 8
np = options.num_cpus
# 4 cpu, 2 clusters
#system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
# physmem = PhysicalMemory(range=AddrRange("512MB")),
# mem2membus = Bus(),
# membus = [Bus(bus_id=i) for i in xrange(2)],
# mem_mode = test_mem_mode,
# l2 = [L2Cache(size='2MB') for i in xrange(np)],
# tol2bus = [Bus() for i in xrange(np)],
# bridge = Bridge())
#
#system.bridge.side_a = system.membus[0].port
#system.bridge.side_b = system.membus[1].port
#
##system.physmem.port = system.mem2membus
#system.physmem.port = system.membus[0].port
#system.physmem.port = system.membus[1].port
#
#for i in xrange(np):
# system.l2[i].cpu_side = system.tol2bus[i].port
# if i < np / 2:
# system.l2[i].mem_side = system.membus[0].port
# else:
# system.l2[i].mem_side = system.membus[1].port
# system.cpu[i].connectMemPorts(system.tol2bus[i])
# system.cpu[i].workload = process
# 2 cpu, 1 cluster
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = PhysicalMemory(range=AddrRange("512MB")),
membus = Bus(),
mem_mode = test_mem_mode
)
system.physmem.port = system.membus.port
for i in xrange(np):
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size='32kB'),L1Cache(size='64kB'))
#system.cpu[i].l2=L2Cache(size='2MB')
#system.cpu[i].tol2bus=Bus()
#system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.port
#system.cpu[i].l2.mem_side = system.membus.port
#system.cpu[i].connectMemPorts(system.cpu[i].tol2bus)
system.cpu[i].connectMemPorts(system.membus)
for i in xrange(np):
system.cpu[i].workload = process
## without cache
#options.num_cpus = 8
#np = options.num_cpus
#system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
# physmem = PhysicalMemory(range=AddrRange("512MB")),
# membus = Bus(),
# mem_mode = test_mem_mode,
# )
#
#system.physmem.port = system.membus.port
#
#for i in xrange(np):
# system.cpu[i].connectMemPorts(system.membus)
# system.cpu[i].workload = process
root = Root(system = system)
Simulation.run(options, root, system, FutureClass)
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