There's no explicit memory controller, so it's effectively FCFS. It shouldn't be too much work to add a scheduler though.
Steve On Fri, May 9, 2008 at 4:52 PM, Lide Zhang <[EMAIL PROTECTED]> wrote: > Hi, > > We were trying to use M5 to build a memory scheduler to change the order of > the memory requests are responded. However, after we looked into the code, > we figured that all the memory accesses are done by calling dram.cc. We were > wondering whether there is any module that explicitly models the memory > scheduler that determines the order and the delay that the requests are > responded by memory. The scheduler should between the bus and the DRAM. > > Thanks. We appreciate your help a lot. > > Sincerely, > > Lide Zhang > > > -- > Lide Zhang > Department of Electronic Engineering > Northwestern University > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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