Hi,
I want to use SE and FS to simulate "hello world" program with multi-core in
m5.
I use se.py as script and the "np = options.num_cpus" is only 1.
How to enable more CPUs in m5 ?
And I want to run "hello world" program in each CPU .
thanks
--------------------------
My script is :
#simple test script for CMP SE
#ding May 2008
# "m5 test.py"
import m5
from m5.objects import *
import os, optparse, sys
#import cpu2000
#m5.AddToPath('../common')
m5.AddToPath('/home/m5_2.0b4/configs/common')
import Simulation
from Caches import *
#import Mybench
import cpu2000
import Benchmarks
#from cpu2000 import ammp
config_path = os.path.dirname(os.path.abspath(__file__))
print config_path
config_root = os.path.dirname(config_path)+"/configs"
print config_root
m5_root = os.path.dirname(config_root)
print m5_root
parser = optparse.OptionParser()
# Benchmark options
parser.add_option("-c", "--cmd",
default=os.path.join(m5_root,
"tests/test-progs/hello/bin/alpha/linux/hello"),
help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
help="The options to pass to the binary, use \" \" around the
entire\
string.")
parser.add_option("-i", "--input", default="",
help="A file of input to give to the binary.")
execfile(os.path.join(config_root, "common", "Options.py"))
(options, args) = parser.parse_args()
process = LiveProcess()
process.executable = options.cmd
process.cmd = [options.cmd] + options.options.split()
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = '2.0GHz'
np = options.num_cpus
print "np=", np
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = PhysicalMemory(range=AddrRange("512MB")),
membus = Bus(), mem_mode = 'timing')
system.physmem.port = system.membus.port
for i in xrange(np):
if options.caches:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '64kB'),
L1Cache(size = '64kB'))
if options.l2cache:
system.l2 = L2Cache(size='2MB')
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
system.cpu[i].connectMemPorts(system.tol2bus)
else:
system.cpu[i].connectMemPorts(system.membus)
system.cpu[i].workload =process
root = Root(system = system)
Simulation.run(options, root, system, FutureClass)
exit_event = m5.simulate()
print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause()
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