Is it possible to quantify the accuracy of the memory timing model with a real piece of hardware? Lets say we put in real numbers for the various latencies and other parameters to make it close to a real SDRAM. Will it be useful to run memory intensive benchmarks and see how the timing numbers match up with those on a real system? (timing correction, batch latency calculation, etc. implemented in the dram.cc)
----- Original Message ----- From: "Steve Reinhardt" <[EMAIL PROTECTED]> To: "M5 users mailing list" <[email protected]> Sent: Monday, June 09, 2008 2:44 PM Subject: Re: [m5-users] passing config parameters to rcS > On Mon, Jun 9, 2008 at 11:25 AM, Sujay Phadke <[EMAIL PROTECTED]> > wrote: >> By the way, is there any effort >> currently to validate the memory timing model? > > None that I know of... the memory timing model is kind of abstract, so > it's not clear what you would validate it against. It's a good idea > though. For the most part it's just been "validated" by looking at > traces and seeing if they make sense, which is admittedly rather > limited. > > Steve > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
