Hi Steve,
I am sorry that I don't exactly understand what you mean. I use the
timing memory model, but I cannot find any "utilization of the bus
between the L2 and memory " in m5stats.txt. I also tried the timing
CPU model and O3 CPU model, and there has no luck. I attach my
configuration.
Thanks a lot,
Meng-Ju
=======================
import m5
from m5.objects import *
import os, optparse, sys
m5.AddToPath('./configs')
import Simulation
from Caches import *
import Mybench
config_path = os.path.dirname(os.path.abspath(__file__))
print config_path
config_root = os.path.dirname(config_path)+"/configs"
print config_root
m5_root = os.path.dirname(config_root)
print m5_root
parser = optparse.OptionParser()
# Benchmark options
parser.add_option("-b", "--benchmark", default="",
help="The benchmark to be loaded.")
parser.add_option("-c", "--chkpt", default="",
help="The checkpoint to load.")
execfile(os.path.join(config_root, "configs", "Options.py"))
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
if options.benchmark == 'perlbench':
process = Mybench.perlbench
elif options.benchmark == 'bzip2':
process = Mybench.bzip2
elif options.benchmark == 'equake':
process = Mybench.equake
elif options.benchmark == 'test':
process = Mybench.test
if options.chkpt != "":
process.chkpt = options.chkpt
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = '2GHz'
np = options.num_cpus
cmt_cpus = [CPUClass(cpu_id = i) for i in xrange(np)]
# ----------------------
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cmt_cpus,
physmem = PhysicalMemory(range=AddrRange("1024MB"),
latency = '200ns'),
membus = Bus(clock='400MHz',width=64), mem_mode='timing')
# ----------------------
# Connect the L2 cache and memory together
# ----------------------
if options.l2cache:
system.l2 = L2Cache(size='4MB')
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
for i in xrange(np):
if options.caches:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
if options.l2cache:
system.cpu[i].connectMemPorts(system.tol2bus)
else:
system.cpu[i].connectMemPorts(system.membus)
system.cpu[i].workload = [process[i]]
system.physmem.port = system.membus.port
root = Root(system = system)
root.system.mem_mode = 'timing'
Simulation.run(options, root, system, FutureClass)
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