This question is not really related to m5 but general multicore design.
Since the number of processors in a multicorer system are constrained by total chip area (400mm^2 for power4 etc), is there a way to estimate the area of O3CPU based on certain parameters like size of LS Queues, reorder buffer size. If anyone knows of methodology or some research regarding this, please give suggestions. _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
