THANK YOU FOR YOUR REPLY!!!
---------------------------------------------
This is my singleDefault.py.
from m5 import *
AddToPath('../')
import Benchmarks
#from MemConfig import *
from FuncUnitConfig import *
## Memory Configuration#################################
## L1Cache configuration ###########
class BaseL1Cache(BaseCache):
size = '32kB'
assoc = 2
block_size = 16
mshrs = 32
tgts_per_mshr = 8
class IL1(BaseL1Cache):
latency = 2* Parent.clock.period
mshrs = 32
class DL1(BaseL1Cache):
latency = 2 * Parent.clock.period
mshrs = 32
## L2Cache configuration ###########
class BaseL2Cache(BaseCache):
size = '1MB'
assoc = '8'
block_size = 32
latency = 4 * Parent.clock.period
mshrs = 64
tgts_per_mshr = 16
class L2(BaseL2Cache):
latency = 4 * Parent.clock.period
mshrs = 32
class BaseL3Cache(BaseCache):
size = '2MB'
assoc = '16'
block_size = 64
latency = 8 * Parent.clock.period
mshrs = 128
tgts_per_mshr = 16
class L3(BaseL3Cache):
latency = 8 * Parent.clock.period
mshrs = 128
class ToL2Bus(Bus):
width = 8
clock = 2 * Parent.clock.period
#energy = 1
class ToL3Bus(Bus):
width = 8
clock = 2 * Parent.clock.period
# energy = 1
class ToMemBus(Bus):
width = 16
clock = 4 * Parent.clock.period
#energy = 1
class SDRAM(BaseMemory):
latency = 100 * Parent.clock.period
uncacheable_latency = 1000 * Parent.clock.period
## CPU Configuration #################################################
class DefaultBranchPred(BranchPred):
pred_class = 'hybrid'
local_hist_regs = '2ki'
local_hist_bits = 11
local_index_bits = 11
local_xor = False
global_hist_bits = 13
global_index_bits = 13
global_xor = False
choice_index_bits = 13
choice_xor = False
ras_size = 16
btb_size = '4ki'
btb_assoc = 4
class DetailedCPU(FullCPU):
icache = IL1(out_bus=Parent.toL2bus)
dcache = DL1(out_bus=Parent.toL2bus)
iq = StandardIQ(size = 64, caps = [0, 0, 0, 0])
iq_comm_latency = 1
fupools = DefaultFUP()
lsq_size = 32
rob_size = 196
rob_caps = [0, 0, 0, 0]
storebuffer_size = 32
width = 8
issue_bandwidth = [8, 8]
prioritized_issue = False
thread_weights = [1, 1, 1, 1]
dispatch_to_issue = 1
decode_to_dispatch = 15
mispred_recover = 3
fetch_branches = 3
ifq_size = 32
num_icache_ports = 1
branch_pred = DefaultBranchPred()
## system configuration ########
class Simple_CMP(Root):
cpu = DetailedCPU()
cpu.workload = Benchmarks.SPECPERLBMKEIO()
cpu.max_insts_all_threads = 1000
toL2bus = ToL2Bus()
toL3bus = ToL3Bus()
toMembus = ToMemBus()
l2 = L2(in_bus=Parent.toL2bus, out_bus=Parent.toL3bus)
l3 = L3(in_bus=Parent.toL3bus, out_bus=Parent.toMembus)
sdram = SDRAM(in_bus=Parent.toMembus)
hier = HierParams(do_data=False, do_events=True)
root = Root(clock='2GHz')
root = Simple_CMP()
2008/6/24 Ali Saidi <[EMAIL PROTECTED]>:
> I have no idea what singleDefault.py is, however I would guess that
> you're trying to create two caches that have the same name.
>
> Ali
>
> On Jun 24, 2008, at 5:37 PM, Ran Qi wrote:
>
> > hi!
> > when ever i try to run the singleDefault.py i get the following
> > message
> > how to solve this problem?
> > Thank you.
> >
> >
> > ../../build/ALPHA_SE/m5.opt -d ./out singleDefault.py
> > M5 Simulator System
> > Copyright (c) 2001-2008
> > The Regents of The University of Michigan
> > All Rights Reserved
> >
> >
> > M5 compiled Jun 23 2008 21:26:16
> > M5 started Tue Jun 24 15:56:58 2008
> > M5 executing on kani.cs.lamar.edu
> > command line: ../../build/ALPHA_SE/m5.opt -d ./out singleDefault.py
> > Traceback (most recent call last):
> > File "<string>", line 1, in ?
> > File "build/ALPHA_SE/python/m5/main.py", line 350, in main
> > File "singleDefault.py", line 6, in ?
> > from BaseCache import *
> > File "/space/ranq/download/m5-2.0b5/src/mem/cache/BaseCache.py",
> > line 3, in ?
> > from MemObject import MemObject
> > File "/space/ranq/download/m5-2.0b5/src/mem/MemObject.py", line 3,
> > in ?
> > class MemObject(SimObject):
> > File "build/ALPHA_SE/python/m5/SimObject.py", line 143, in __new__
> > AssertionError
> >
> > _______________________________________________
> > m5-users mailing list
> > [email protected]
> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>
> _______________________________________________
> m5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>
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