There are some problems with the prefetching support in the new memory system... basically it did not get tested after the rewrite. There were some patches posted to the mailing list recently that I will be pushing to the development repository soon.
Steve On Mon, Jul 21, 2008 at 10:31 AM, Gary Chai <[EMAIL PROTECTED]> wrote: > Hi all: > I want to take a look at the result of prefetch, so I add two lines in the > configs/example/fs.py and keep others same. > > if options.l2cache: > test_sys.l2 = L2Cache(size = '2MB') > test_sys.tol2bus = Bus() > test_sys.l2.cpu_side = test_sys.tol2bus.port > test_sys.l2.mem_side = test_sys.membus.port > test_sys.l2.prefetch_policy = 'tagged' #### by me > test_sys.l2.prefetch_miss = 'true' #### by me > > Then the simulation is aborted and the following is the error. > > M5 compiled Jun 9 2008 21:51:22 > M5 started Mon Jul 21 13:24:26 2008 > M5 executing on seasmile-pc > command line: /home/m5/m5-2.0b5/build/ALPHA_FS/m5.debug -d result2 > /home/m5/m5-2.0b5/configs/example/fs.py -t --caches -n 1 --l2cache -b hello > Global frequency set at 1000000000000 ticks per second > warn: kernel located at: /dist/m5/system/binaries/vmlinux > 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 > 2009 > Listening for system connection on port 3456 > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > **** REAL SIMULATION **** > warn: Entering event queue @ 0. Starting simulation... > m5.debug: build/ALPHA_FS/mem/cache/base.hh:471: void > BaseCache::deassertMemSideBusRequest(BaseCache::RequestCause): Assertion > `false' failed. > Program aborted at cycle 12851847000 > Aborted > > Can you help me find the reason? > Thanks > Gary > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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