I see that for the l2bus, but the l1cache does not have such a width. It appears that the entire cache line (packet) is sent at once to the cpu.
-Rick nathan binkert wrote: > All busses have a width parameter. Check out config.ini. > > Nate > > On Wed, Aug 27, 2008 at 3:00 PM, richard strong <[EMAIL PROTECTED]> wrote: > >> Hi, >> >> I am trying to determine the bus width of the bus connected to a cache. >> Is this just the address range of the port connected to the cache? >> >> -Rick >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> >> >> > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
