In it's default mode (atomic memory transactions with a simple cpu) M5 simulates a perfect memory system with a 1 CPU cycle latency to memory. It this case the time (in ticks) to execute the benchmark is equal to the number of instructions/cpu width * 1/frequency. For other results you'll need a timing memory model. You can use the simple timing cpu or the O3 cpu (Gabe does the O3 cpu worth with X86 SE?). Then the time to run the benchmark will vary based of the system parameters. Look at the -t, -d, --caches, --l2cache options to se.py.
As for a page on the wiki, I don't believe there is one. Please feel free to contribute what you've learned, however. Ali On Oct 22, 2008, at 3:43 PM, Ananth wrote: > Hi all > I am trying to understand the output that M5 produces. I am running my > program with m5 (v2.05) in x86 Syscall emulation mode. > At the end of the simulation M5 writes a line that says that 'Target > exited at cycle xyz since it called exit()'. The value xyz reported > corresponds to the sim_ticks value in m5stats.txt. What I noticed is a > 1-1 correlation between CPU frequency / CPU width and the sim_ticks > value. > > What I mean is this: For a fixed workload, if I double the frequency > or width values, the sim_ticks value reported at the end of the > simulation is reduced by half. > Which stat should I be using it as a measure of performance? > > Is there a page on the m5 wiki that gives details on the output stats > and the way to interpret it? I wasn't able to locate any. > > -- > Ananth Narayan S > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
