On Tue, Nov 11, 2008 at 12:28 AM, srimugunthan dhandapani < [EMAIL PROTECTED]> wrote:
> hi, > Can somebody share the python script file to do the sampling for switching > between CPU models periodically > for the following way of simulation > > |------------FF----------------|--cacheW-|----detailed---|------------FF----------------|--cacheW-|----detailed---| > . . .. ..etc > > for fixed Fast forward interval , cache warming interval, detailed > simulation interval > Thanks, > Mugunthan > Hi all , I read this thread http://thread.gmane.org/gmane.comp.emulators.m5.users/907/focus=925 and based on that I tried to modify the python script and try to run the test in syscall emulation mode. But I get the following error ****** M5 started Nov 21 2008 04:23:53 M5 executing on srimugunthan-laptop command line: build/ALPHA_SE/m5.debug configs/se_my/run.py -c cc1.alpha -o 1stmt.i Global frequency set at 1000000000000 ticks per second panic: only one workload allowed @ cycle 0 [create:build/ALPHA_SE/cpu/simple/timing.cc, line 859] Program aborted at cycle 0 Aborted (core dumped) ********** I run in syscall emulation mode an alpha executable cc1.alpha with input 1stmt.i the command line is build/ALPHA_SE/m5.debug configs/se_my/run.py -c cc1.alpha -o "1stmt.i" Can somebody help me solve this problem My run.py script is as follows . ********* # Get paths we might need. It's expected this file is in m5/configs/example. config_path = os.path.dirname(os.path.abspath(__file__)) config_root = os.path.dirname(config_path) m5_root = os.path.dirname(config_root) parser = optparse.OptionParser() # Benchmark options parser.add_option("-c", "--cmd", default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"), help="The binary to run in syscall emulation mode.") parser.add_option("-o", "--options", default="", help='The options to pass to the binary, use " " around the entire string') parser.add_option("-i", "--input", default="", help="Read stdin from a file.") parser.add_option("--output", default="", help="Redirect stdout to a file.") parser.add_option("--errout", default="", help="Redirect stderr to a file.") execfile(os.path.join(config_root, "common", "Options.py")) (options, args) = parser.parse_args() if args: print "Error: script doesn't take any positional arguments" sys.exit(1) if options.bench: try: if m5.build_env['TARGET_ISA'] != 'alpha': print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time" sys.exit(1) exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench) process = workload.makeLiveProcess() except: print >>sys.stderr, "Unable to find workload for %s" % options.bench sys.exit(1) else: process = LiveProcess() process.executable = options.cmd process.cmd = [options.cmd] + options.options.split() if options.input != "": process.input = options.input if options.output != "": process.output = options.output if options.errout != "": process.errout = options.errout if options.detailed: #check for SMT workload workloads = options.cmd.split(';') if len(workloads) > 1: process = [] smt_idx = 0 inputs = [] outputs = [] errouts = [] if options.input != "": inputs = options.input.split(';') if options.output != "": outputs = options.output.split(';') if options.errout != "": errouts = options.errout.split(';') for wrkld in workloads: smt_process = LiveProcess() smt_process.executable = wrkld smt_process.cmd = wrkld + " " + options.options if inputs and inputs[smt_idx]: smt_process.input = inputs[smt_idx] if outputs and outputs[smt_idx]: smt_process.output = outputs[smt_idx] if errouts and errouts[smt_idx]: smt_process.errout = errouts[smt_idx] process += [smt_process, ] smt_idx += 1 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) CPUClass.clock = '2GHz' np = options.num_cpus system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], physmem = PhysicalMemory(range=AddrRange("512MB")), membus = Bus(), mem_mode = test_mem_mode) system.physmem.port = system.membus.port if options.l2cache: system.l2 = L2Cache(size='2MB') system.tol2bus = Bus() system.l2.cpu_side = system.tol2bus.port system.l2.mem_side = system.membus.port for i in xrange(np): if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) if options.l2cache: system.cpu[i].connectMemPorts(system.tol2bus) else: system.cpu[i].connectMemPorts(system.membus) system.cpu[i].workload = process if options.fastmem: system.cpu[0].physmem_port = system.physmem.port cpu = AtomicSimpleCPU() test_mem_mode = 'atomic' cpu.clock = '2GHz' switch_cpu = TimingSimpleCPU(defer_registration=True) system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus(),mem_mode = test_mem_mode) system.physmem.port = system.membus.port system.cpu.workload = process root = Root(system = system) root.system.cpu = cpu root.switch_cpu = switch_cpu root.switch_cpu.connectMemPorts(root.system.membus) root.switch_cpu.mem = root.system.physmem cpu_list1 = [(cpu,switch_cpu)] cpu_list2 = [(switch_cpu,cpu)] cpu.connectMemPorts(root.system.membus) cpu.mem = root.system.physmem if options.maxtick: maxtick = options.maxtick elif options.maxtime: simtime = m5.ticks.seconds(simtime) print "simulating for: ", simtime maxtick = simtime else: maxtick = m5.MaxTick m5.instantiate(root) if options.fast_forward: m5.stats.reset() i = 0 phase = 1 while i < 5: print "m5.simulate for 500 cycles" exit_event = m5.simulate(500) if phase == 1: print "Switching CPUs" m5.switchCpus(cpu_list1) phase=2 elif phase == 2: print "Switching CPUs 2nd phase" m5.switchCpus(cpu_list2) phase = 1 i = i + 1 exit_event = m5.simulate(maxtick) if exit_cause == '': exit_cause = exit_event.getCause() print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) ************
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