Hello, I have a system with 4 cpu and one L2 cache shared with all of the cores, I am doing the simulations with the detail cpu. I am interested in study how the cores access to the shared cache. I have been looking in the code of mem/bus.cc and mem/bus.hh. In the file bus.cc there is a function called recvTiming, this is the function that is used to access to the bus and when the bus is busy the accesses are stored in a retryList, but my question is: is this the function used to access to the shared cache? or it is used only to access to the main memory. I have been printing the accesses in the retryList , but I do not see enough access from the different cores, that's why I am thinking that maybe that retryList is not the retryList for the shared cache.
And another question is there a way to assign a core per program in full system mode, I know that is a linux question and not a M5 simulator problem, but I would like to know if anybody knows a way to assign a program to each core. Thank you. _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
