Hello, I am exploring the circulation of packages along the bus using the Bus flag and some information that I am printing, and I have several questions, I am using the detailed cpu and the configuration that comes with the se.py file, with --caches and --l2cache options.
I am printing the origin of the cpu with pkt->req->contextId(), and I get outputs likes this: CPU: 1 <-> src_port: 1, SRC: 1 DEST: -1, here we see the cpu number, the src_port ( pkt->getSrc() ) and the destination ( pkt->getDest() ) 70000: system.membus: recvTiming: src 1 dst -1 ReadReq 0x1aa180 70000: system.membus: The bus is now occupied from tick 70000 to 71000 CPU: 1 <-> src_port: 0, SRC: 0 DEST: 1 100000: system.membus: recvTiming: src 0 dst 1 ReadResp 0x1aa180 100000: system.membus: The bus is now occupied from tick 100000 to 102000 CPU: 1 <-> src_port: 8, SRC: 8 DEST: 6 162500: system.tol2bus: recvTiming: src 8 dst 6 ReadResp 0x1aa180 162500: system.tol2bus: The bus is now occupied from tick 162500 to 175000 162500: system.tol2bus: Remove retry from list 8 Can anyone tell me why for the same cpu there are several different origin ports?, I guess is because the cpu is connected to several buses with different ports, maybe one for the cache and another one for the main memory, but can anyone confirm this?. but if this is right I do not understand why if the port 1 is for the membus why I see after port 0 also for the membus, can anyone please clarify this?. And also is there anyway to identificate the ports?, if one is for the cache and another one for the memory is there any way to tell wich one is for the cache and one for the memory?. Regarding the destination I have a similar question, is there any way to identify id's (pkt->getDest() ) with high level information such as, main memory, L2 cache..., thank you. Thanks in advance. _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
