The python configuration is only processed once at the beginning of the simulation when the equivalent C++ configuration is set up (specifically in the call to m5.instantiate(root)). Changing the python config after that point will have no effect as you saw.
Even if you did change the C++ cache configuration on the fly it would die horribly due to coherence problems (e.g., all the dirty blocks in those caches that are no longer part of the system). You would have to flush the dirty all of the caches you are disabling before you make the change (or leave them connected enough to continue to snoop). Steve On Thu, Feb 12, 2009 at 4:00 PM, Xi Chen <[email protected]> wrote: > Hi all, > > Is it possible that I can reconfigure the cache hierarchy during runtime > in M5? For example, say initially I have a three-level cache hierarchy, > i.e., cpu->L1->L2->L3->off-chip memory, after simulating a few cycles, I > want to disable L1 and connect cpu directly to L2. Is that doable? > > I tried something like this after simulating 1 million cycles. But it > failed somehow. > > test_sys.cpu[0].icache = l1_ic # reconnect cpu to l1 icache > test_sys.cpu[0].dcache = l1_dc # reconnect cpu to l1 dcache > test_sys.cpu[0].icache_port = l1_ic.cpu_side > test_sys.cpu[0].dcache_port = l1_dc.cpu_side > test_sys.cpu[0].icache.mem_side = test_sys.cpu[0].toL2Bus.port[0] > test_sys.cpu[0].dcache.mem_side = test_sys.cpu[0].toL2Bus.port[1] > > It looked to me that even after reconnecting the ports, the statistics > for L1 instruction cache and data cache still keep increasing... > > Thank you, > --Xi > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
_______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
