Hi Steve It would be a great help for me if you can provide me those patch about the caches and also how to apply that patches so that I can continue my research work without this interruption
Thanks Ashutosh Jain On Sat, Feb 14, 2009 at 6:19 PM, Steve Reinhardt <[email protected]> wrote: > There are a number of bugs in the prefetcher currently... we received some > patches from the list a while ago, and I have applied those patches and > fixed several others in my internal tree, but haven't had the chance to push > those to the public repository yet. I'll try and put that higher on my > to-do list. > > Steve > > On Thu, Feb 12, 2009 at 4:30 PM, Ashutosh Jain <[email protected]>wrote: > >> Hi >> >> I am trying to run ghb prediction applied over L3 cache. While running the >> simulation, I have following configuration on L3 cache which is depicted on >> config.ini which I got after simulation. >> >> Part of config.ini containing info for L3 cache where I have used >> prefetch_policy to be ghb ::: >> >> type=BaseCache >> addr_range=0:18446744073709551615 >> assoc=16 >> block_size=64 >> cpu_side_filter_ranges= >> hash_delay=1 >> latency=8000 >> lifo=false >> max_miss_count=0 >> mem_side_filter_ranges= >> mshrs=30 >> prefetch_access=false >> prefetch_cache_check_push=true >> prefetch_data_accesses_only=true >> prefetch_degree=10 >> prefetch_latency=800000 >> prefetch_miss=true >> prefetch_past_page=true >> prefetch_policy=ghb >> prefetch_serial_squash=true >> prefetch_use_cpu_id=true >> prefetcher_size=1000 >> prioritizeRequests=false >> repl=Null >> size=2097152 >> split=false >> split_size=0 >> subblock_size=0 >> tgts_per_mshr=12 >> trace_addr=0 >> two_queue=false >> write_buffers=8 >> cpu_side=system.tol3aBus.port[0] >> mem_side=system.membus.port[1] >> >> I am getting the statistics for l3 cache overall miss rate. But the point >> is its showing the same value unchanges on both the cases - when I have >> applied ghb prefetch technique and and when I haven't applied any prediction >> technique. I am in whimsical situation *why the two simulations(one with >> prediction technique and other without the prediction technique) gives the >> same value for l3 cache miss rate*...... >> >> >> Thanks is advance >> >> -- >> Ashutosh Jain >> >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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