Hi, nathan,thanks for your reply. The bit that marks the address as an uncached access is 43 bit, in the 0xffff fdxx xxxx xxxx that you mentioned, it's the highest bit of the "d". I supposed that the 0xffff fcff ffff ffff is the address mask.
In this cace, how should I specify an uncached access address ? Can I specify the address like this: 0xffff f8xx xxxx xxxx and the mask is 0xffff f7ff ffff ffff ? Thank you ! > > > You have to be careful to differentiate the physical address space > from the virtual address space. The stuff you got from isa_traits.hh > is virtual address space and describes the superpage stuff that you > can find in the processor documentation. the address with the high > bit set that you've described is a physical address (with the high bit > set so you can do an uncached access. > > Assuming that you want to do an uncached access to a specific physical > address, you're probably going to want an address that looks like > 0xfffffdxxxxxxxxxx. The 0xfffffc part is the K0Seg super page. The > bit that turns the 'c' into a 'd' should be the uncacheable bit. You > can look through the configuration files to find other examples of > uncached addresses. > > Nate > > On Sun, Mar 1, 2009 at 7:41 AM, Veydan Wu <[email protected]> wrote: > > Hi all, Is the address space identical to the tsunami system address > space, > > which is from the 0x800 0000 0000 is the space for PIO, the low 4G space > is > > system memory ? > > > > ?I read the arch/alpha/isa_trait.h and got this: > > > > // User Virtual > > const Addr USegBase = ULL(0x0); > > const Addr USegEnd = ULL(0x000003ffffffffff); > > > > // Kernel Direct Mapped > > const Addr K0SegBase = ULL(0xfffffc0000000000); > > const Addr K0SegEnd = ULL(0xfffffdffffffffff); > > > > // Kernel Virtual > > const Addr K1SegBase = ULL(0xfffffe0000000000); > > const Addr K1SegEnd = ULL(0xffffffffffffffff); > > > > Every time I write something into 0x801 0000 0000, which is a valid PIO > > address according to tsunami handbook, a segmentation fault occur. > > > > This is a bit different from the one above, did I miss anything? > > > > Thank you ! > > > > > > _______________________________________________ > > m5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > > ------------------------------ > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > End of m5-users Digest, Vol 32, Issue 1 > *************************************** >
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