this is correct.
On Thu, Mar 12, 2009 at 6:21 PM, Veydan Wu <[email protected]> wrote: > Hi Steve, thanks for your reply. Do you mean that the bridge is used to > connect membus and iobus, and the cache is connected to the membus directly? > In this case, The bridge is between the iobus and membus, is that right ? > Thank you ! > >> >> Message: 4 >> Date: Thu, 12 Mar 2009 06:07:18 -0800 >> From: Steve Reinhardt <[email protected]> >> Subject: Re: [m5-users] A question about memory bus >> To: M5 users mailing list <[email protected]> >> Message-ID: >> <[email protected]> >> Content-Type: text/plain; charset=ISO-8859-1 >> >> A bridge is only needed to connect two buses. Anything that's not a >> bus can connect directly to a bus. >> >> Steve >> >> On Thu, Mar 12, 2009 at 1:02 AM, Veydan Wu <[email protected]> wrote: >> > Hi, all, when the fs.py making a LinuxAlphaSystem which it invoke a >> > function >> > makeLinuxAlphaSystem in FSConfig.py, there is a bridge connecting membus >> > and >> > iobus.? But in fs.py, the cache is connected directly to membus, so >> > where is >> > the bridge ?? Sorry for such silly question, but it really confuse me. >> > Thanks ! >> > >> > _______________________________________________ >> > m5-users mailing list >> > [email protected] >> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > >> >> > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
