With the bus model, all the devices are probed atomically to determine who the responder will be in regards to the coherence model. First all the devices that need to be snooped will be probed first(in you're the L2's), the responder then sets a flag on the pkt called memInhibit (the L2 that will supply the Owned/Modified line to the load miss). When the L3 is probed by the bus, it sees the memInhibit flag is set and returns without doing the access, so this is how the L3 is informed a cache to cache transfer is being done. Hope this helps.
Geoff -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Shoaib Akram Sent: Monday, May 11, 2009 12:15 PM To: [email protected] Subject: [m5-users] Snooping / Simultaneous Lookups in multiple Levels Suppose I have multiple L2 caches connected via shared bus and a single shared L3. Also a load miss in one of L2s is served by another L2 (cache-to-cache transfer). How/when is the L3 informed regarding the cache-to-cache transfer? Is it accessed simultaneously and later inhibited after some time? _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users No virus found in this incoming message. Checked by AVG - www.avg.com Version: 8.5.287 / Virus Database: 270.12.23/2106 - Release Date: 05/11/09 05:52:00 _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
