Varying the latency between simulations. As an example, if for a 4-way
CMP, the average cache to cache (both LOAD and STORE) transfer latency is
50 cycles, I want to see the performance impact if the average latency
goes down to 40 cycles.


> This would be better served on the mailing list [email protected].
>
>
>
> The short answer is yes, M5 does do cache to cache transfers for a CMP.
>
>
>
> By varying the latency, what do you mean? Varying the latency during
> simulation, or between simulations?
>
>
>
>
>
>
>
> I am new to m5. Could you please tell me what m5 does in case of LOAD for
> shared cache line. Basically I need a CMP system with private L2 caches,
> and
> in case
> of LOAD, the request should be satisfied by peer L2 caches (of course if
> it
> is available) instead of going to memory. I want to vary the latency for
> cache to cache transfer.
> Does the current coherence in m5 work this way?? Or, how hard will it be
> to
> change?
>
> thanks
>
> --
> Md. Kamruzzaman (Shawon)
> Graduate Student
> Computer Science and Engineering Department
> University of California, San Diego (www.cse.ucsd.edu)
> Member, Elite Problemsetters' Panel, VOJ, Spain
> Homepage:  http://www.cse.ucsd.edu/users/mkamruzz
>
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-- 
Md. Kamruzzaman (Shawon)

Graduate Student
CSE Dept., University of California, San Diego
Cell# 858-205-9350
Homepage: http://www.cse.ucsd.edu/users/mkamruzz
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