Not built in... you would have to hack that in. You probably want to do it in the bus model (src/mem/bus.cc).
Steve On Tue, Jun 9, 2009 at 10:07 AM, Ashutosh Jain <[email protected]> wrote: > > Hi > I am interested in performing the trace for the data flow(blocks) between > main memory and the L3 cache; between L2 and L3 cache. So is there any > methodology in M5 to do that like dump trace the data into a file or to > carry out the trace. > > Thanks in advance > Ashutosh Jain > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
_______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
