> One more quick clarification: >> You response to my first question seems to suggest that the current >> infrastructure supports SMT on SE mode for SPARC and/or ALPHA as long >> as I limit the number of s/w threads to the number of h/w threads? Is >> that correct? > > > I believe that's true, yes, though it's not a configuration I've used > personally. If anyone else knows otherwise please speak up. >
This should be true. The regression tests have been limited to ALPHA and arent exhaustive as of yet. I plan to start updating the SMT regressions (for ALPHA) in mid-July (really swamped right now) so you can keep tabs on the m5-dev email list for progress. This is definitely an area that needs to be tightened a bit. As for SPARC, make sure that once you compile that you account for the # of registers needed (incl. register windows). An assertion will be triggered if that's not configured correctly. But the implementation of SMT otherwise should be ISA independent. As always, if you run into some problems with SMT or interpreting how it works email the appropriate m5-users and m5-dev lists. -- - Korey
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