It's required to have an I/O cache that bridges the a non-coherent I/O device to the coherent part of the memory system. This is roughly what is going on the real system since something has to coherently get a line when the device is not writing the entire block.
Ali On Thu, 2 Jul 2009 15:10:05 -0500 (CDT), Shoaib Akram <[email protected]> wrote: > In the Tsunami system modeled, iocache is for optimization ? One can safely > remove it and expect no anomaly. Or is it the source of communication b/w > I/O sub-systm and processer caches? > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
