Hello all, I want to track physical register accesses in a single core of an ultrasparc/opensparc T1 (which has SMT support for 4 h/w threads, each of which is allocated a quarter of the physical register file).
It appears that the way to model this in m5 is to: 1. Instantiate one master physical register file with the total integer registers (and , perhaps, even floating point registers) required for all the 4 threads. Assert statements in cpu.cc suggest that. assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2. The current rename logic doesn't seem to track the actual mapping between the physical register file and the isa register file across the h/w threads. If that is correct, the rename logic should be modified so that register renaming for each thread takes place to physically separate portions of the master physical register file. Could someone comment on my understanding above. regards, Soumyaroop. -- Soumyaroop Roy Ph.D. Candidate Department of Computer Science and Engineering University of South Florida, Tampa http://www.csee.usf.edu/~sroy <http://www.csee.usf.edu/%7Esroy>
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