There are a few problems with doing things this way. First, there are no guarantees that SMT is supported for SPARC on O3 as far as I know. Someone with more experience with O3 and SMT would have to comment there, but the fact that there are no regressions for it suggests that it's at least untested.
Second, I don't know if all the binaries that regression needs are going to be available for SPARC. If it just uses the "hello" binary then that might work out. Third, if the binary exists and runs correctly, copying the reference outputs from alpha to sparc will almost certainly not be what you want. The many detailed statistics O3 tracks will definitely change when a completely different binary compiled for another architecture is used. Quoting soumyaroop roy <[email protected]>: > Thanks for your replies. > > All I did were the following (from <m5-root-dir>): > > 1. Made a copy of the test (although this appears to serve only as gold > ouputs): > % cp -r tests/quick/01.hello-2T-smt/ref/alpha > tests/quick/01.hello-2T-smt/ref/sparc > > 2. Ran the testcase: > % scons build/SPARC_SE/tests/fast/quick/01.hello-2T-smt > > What steps should I take to debug this further? > > regards, > Soumyaroop. > > On Mon, Jul 13, 2009 at 8:20 PM, Steve Reinhardt <[email protected]> wrote: > >> It's also a sign of a deadlock... perhaps there's a deadlock situation >> that's not covered by the assertion. >> >> Steve >> >> >> On Mon, Jul 13, 2009 at 3:31 PM, Cong Wang <[email protected]> wrote: >> >>> The error suggests that you do not have anything on the main event >>> queue. Please check if you are making the proper call to schedule >>> events correctly on the main event queue. >>> >>> Regards >>> James Wang >>> >>> On Mon, Jul 13, 2009 at 3:12 PM, soumyaroop roy<[email protected]> wrote: >>> > Hello all, >>> > >>> > I tried to run the testcase 01.hello-2T-smt for SPARC without increasing >>> the >>> > number of physical registers (in o3-timing.py script) and I was hoping >>> to >>> > see an assertion failure because of the following statement in cpu.cc: >>> > assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); >>> > >>> > However, I get no such failure. Instead, I get this error: >>> > "Exiting @ tick 9223372036854775807 because simulate() limit reached" >>> > >>> > Here are the contents of simout (numThreads and TheISA::NumIntRegs are >>> also >>> > printed out): >>> > </fast/quick/01.hello-2T-smt/sparc/linux/o3-timing$ more simout >>> > M5 Simulator System >>> > >>> > Copyright (c) 2001-2008 >>> > The Regents of The University of Michigan >>> > All Rights Reserved >>> > >>> > >>> > M5 compiled Jul 13 2009 16:27:20 >>> > M5 revision 94c016415053+ 6283+ default tip >>> > M5 started Jul 13 2009 18:03:38 >>> > M5 executing on theoracle >>> > command line: build/SPARC_SE/m5.fast -d >>> > build/SPARC_SE/tests/fast/quick/01.hello-2T-smt/sparc/linux/o3-timing >>> -re >>> > tests/run.py >>> > build/SPARC_SE/tests/fast/quick/01.hello-2T-smt/sparc/linux/o3-timing >>> > Global frequency set at 1000000000000 ticks per second >>> > numThreads: 2 >>> > numIntRegs: 169 >>> > numFloatRegs: 64 >>> > info: Entering event queue @ 0. Starting simulation... >>> > Exiting @ tick 9223372036854775807 because simulate() limit reached >>> > >>> > While my simerr is this: >>> > </fast/quick/01.hello-2T-smt/sparc/linux/o3-timing$ more simerr >>> > warn: Sockets disabled, not accepting gdb connections >>> > For more information see: http://www.m5sim.org/warn/d946bea6 >>> > >>> > What am I doing wrong here? >>> > >>> > regards, >>> > Soumyaroop. >>> > >>> > -- >>> > Soumyaroop Roy >>> > Ph.D. Candidate >>> > Department of Computer Science and Engineering >>> > University of South Florida, Tampa >>> > http://www.csee.usf.edu/~sroy <http://www.csee.usf.edu/%7Esroy> >>> > _______________________________________________ >>> > m5-users mailing list >>> > [email protected] >>> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> > >>> >>> >>> >>> -- >>> Regards >>> James Wang >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >> >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > > -- > Soumyaroop Roy > Ph.D. Candidate > Department of Computer Science and Engineering > University of South Florida, Tampa > http://www.csee.usf.edu/~sroy > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
