one way, might catch such packets on the system bus. Packet has a fields that would tell the command(load/store) and address that generated the request.
---- Original message ---- >Date: Tue, 13 Oct 2009 16:41:48 -0400 >From: Felix Loh <[email protected]> >Subject: [m5-users] Tracing loads/stores that miss in the L2 cache >To: "[email protected]" <[email protected]> > >Hello, > >I was wondering, is there a way to get a trace of only the memory >operations (loads and stores) that miss in the L2 cache (i.e those >that need to access main memory)? I'm currently using the AtomicSimple >CPU model. > >Thanks, >Felix >_______________________________________________ >m5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
