Hey,

Since I modified the python-scripts a little bit it will be difficult to execute the exact same command line as I do. However I'm using build/ALPHA_SE/m5.opt -d simulator-out/8stagesAlt/hello/inorder --trace-file=tracedump --trace-flags=AddrDep configs/config-max/max.py --inorder --caches --exe=benchmarks/hello/hello --cmd=hello -output=simulator-out/8stagesAlt/hello/inorder/bench.out --errout=simulator-out/8stagesAlt/hello/inorder/bench.errout

The address 0x120000d70 is maybe a better example: It gets added a lot of times but never gets removed (or maybe once). At tick 1697000 the instruction gets added to the dependency list, and at tick 1698000 the instruction gets squashed.

You'll probably need my configuration for this, since the ticks might be different, thats why I added the config-file. (You might note that some parameters were set to unrealistic values. However the problem also occured for normal values, in case you would wonder :-)

Most of the addresses are indeed added to the list more than once (but get removed only once)!
Some of the addresses are added to the list once, and never removed.
(I built a small program to identify the adresses that get added but not removed, if you are interested I can send it to you).

What do you mean with a time sync?

Thanks!

Max

On 03/12/2010 05:29 PM, Korey Sewell wrote:
Hi Max,
thanks for further investigating. it does look like the mismanagement of that function is a "time sync".

    Take for example instruction 0x12000067c. This one is added to
    addrList, a little bit later a squash occurs and this instruction
    never gets removed!  This never happens in the case of 5 pipeline
    stages.
    If you want I can give you all instructions that aren't removed..

Can you provide the command line you're using as well as the simulation ticks in which you witness the above error?

I would guess either something is not catching in that squash() function OR somehow the same addresses are getting added to that list more than once.

An assertion on some reasonable address list size will eventually be a good bug catcher as well.

- Korey


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[root]
type=Root
children=system
dummy=0

[system]
type=System
children=cpu membus physmem
mem_mode=timing
physmem=system.physmem

[system.cpu]
type=InOrderCPU
children=dcache dtb icache itb tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
dataMemPort=dcache_port
defer_registration=false
div16Latency=3
div16RepeatRate=1
div24Latency=3
div24RepeatRate=1
div32Latency=3
div32RepeatRate=1
div8Latency=3
div8RepeatRate=1
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchMemPort=icache_port
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=50000000
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=3
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
progress_interval=0
stageTracing=false
stageWidth=1
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side

[system.cpu.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=65536
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.membus.port[2]

[system.cpu.dtb]
type=AlphaTLB
size=64

[system.cpu.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=500
max_miss_count=0
mshrs=10
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=5000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.membus.port[1]

[system.cpu.itb]
type=AlphaTLB
size=48

[system.cpu.tracer]
type=ExeTracer

[system.cpu.workload]
type=LiveProcess
cmd=simple2-ALPHA
cwd=
egid=100
env=
errout=/home/mbreughe/m5/dev/simulator-out/8stagesAlt/simple2-ALPHA/inorder/bench.errout
euid=100
executable=benchmarks/simple/simple2-ALPHA
gid=100
input=benchmarks/simple/input
max_stack_size=67108864
output=/home/mbreughe/m5/dev/simulator-out/8stagesAlt/simple2-ALPHA/inorder/bench.out
pid=100
ppid=99
simpoint=0
system=system
uid=100

[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.icache.mem_side 
system.cpu.dcache.mem_side

[system.physmem]
type=PhysicalMemory
file=
latency=2000
latency_var=0
null=false
range=0:2147483647
zero=false
port=system.membus.port[0]

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