retireHead() sounds right (since you can only retire/commit an instruction in program order), but you should always double check the code to verify things.
On Wed, May 12, 2010 at 3:20 PM, Eberle <[email protected]> wrote: > Korey, > > I mean the order defined by the compiled program. > > In ROB, you mean to check the retireHead method? > > > -- > Eberle A. Rambo. > > > > On Tue, May 11, 2010 at 3:43 PM, Korey Sewell <[email protected]> wrote: > >> By program order, I assume you mean the order the instructions are >> committed in. >> >> If you are post-processing this data, you can always turn on the Exec flag >> to see the ordering. >> >> If you need this data in the middle of the simulation, you should be able >> to look in the ROB, where out of order processors typically keep the >> sequential order of instructions. >> >> >> On Tue, May 11, 2010 at 2:05 PM, Eberle <[email protected]> wrote: >> >>> Where can the program order be captured in a O3 cpu? >>> Maybe in the IEW? >>> >>> -- >>> Eberle Rambo. >>> >>> >>> >>> On Wed, May 5, 2010 at 9:04 AM, Eberle <[email protected]> wrote: >>> >>>> Thanks for the answer. >>>> I need to log every write and read instruction when it is issued by the >>>> processor. Both write and read with address and data. >>>> In the AtomicSimpleCPU I already found where to get that information. >>>> Could you give me a hint to do this in the O3? >>>> I'm looking into the cpu.hh, LSQ and LSQ unit, but I need to be sure. >>>> >>>> Using Sparc_SE. >>>> >>>> >>>> -- >>>> Eberle A. Rambo. >>>> >>>> >>>> >>>> On Tue, May 4, 2010 at 6:46 PM, Steve Reinhardt <[email protected]>wrote: >>>> >>>>> As far as I know, the O3 model has only been used extensively with >>>>> Alpha, particularly in multiprocessor systems. (Someone please speak >>>>> up if you've used it with another ISA in MP modeling.) As a result, >>>>> O3 has only been designed to support Alpha's weak memory model. If >>>>> whatever it does is sufficient for TSO or PSO that's purely >>>>> coincidence. One thing that would need to be added for some stronger >>>>> models (certainly for SC) is that invalidations forwarded from the L1 >>>>> dcache up to the CPU, which are currently dropped on the floor, would >>>>> need to be handled in order to invalidate speculative loads as well. >>>>> >>>>> Steve >>>>> >>>>> On Tue, May 4, 2010 at 11:46 AM, Gabriel Michael Black >>>>> <[email protected]> wrote: >>>>> > I don't remember either myself or anyone else implementing anything >>>>> to >>>>> > change the memory model implemented by O3, so I'm pretty sure it's >>>>> going to >>>>> > be the same no matter what. I'm not sure which of the SPARC memory >>>>> models it >>>>> > corresponds to, though. The configuration of the memory system itself >>>>> might >>>>> > also partially determine that. Could someone that knows the memory >>>>> system >>>>> > better comment? >>>>> > >>>>> > Gabe >>>>> > >>>>> > Quoting Eberle <[email protected]>: >>>>> > >>>>> >> Does the Sparc O3 processor implement the specified memory model? In >>>>> this >>>>> >> case, TSO and optionally PSO. >>>>> >> Or is the program executed sequentially? >>>>> >> >>>>> >> If yes, does the simple processor model also implement it? >>>>> >> >>>>> >> >>>>> >> Thanks in advance, >>>>> >> >>>>> >> -- >>>>> >> Eberle A. Rambo. >>>>> >> >>>>> > >>>>> > >>>>> > >>>>> > _______________________________________________ >>>>> > m5-users mailing list >>>>> > [email protected] >>>>> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>>>> > >>>>> _______________________________________________ >>>>> m5-users mailing list >>>>> [email protected] >>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>>>> >>>> >>>> >>> >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >> >> >> >> -- >> - Korey >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- - Korey
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