Hello Eberle: On Tue, Jun 22, 2010 at 10:04 AM, Eberle <rambo.u...@gmail.com> wrote: > I've read the thread about SPARC_FS and InOrderCPU, but I need to know > whether it works with SPARC_SE.
Currently, SPARC ISA is not supported in InOrderCPU (http://m5sim.org/wiki/index.php/InOrder_ToDo_List). FS is currently not supported for any ISA. > > > And also: The TimingSimpleCPU is equivalent to InOrderCPU, in terms of > pipeline and memory access (reordering)? TimingSimpleCPU does not model a CPU pipeline. Please refer to the documentation of these CPUs here: TimingSimpleCPU: http://m5sim.org/wiki/index.php/SimpleCPU InOrderCpu: http://m5sim.org/wiki/index.php/InOrder > > > > -- > Eberle A. Rambo. regards, Soumyaroop > > _______________________________________________ > m5-users mailing list > m5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- Soumyaroop Roy Ph.D. Candidate Department of Computer Science and Engineering University of South Florida, Tampa http://www.csee.usf.edu/~sroy _______________________________________________ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
