Any help?
Thanks.
On 2010/7/13 18:32, Wang, Weixun wrote:
Hi m5-uer list,
(I also posted this thread on m5-dev list. Sorry for any of you who
received it twice!)
My understanding of the cache subsystem in M5 is that all caches (L1s
in all cores and L2 in a CMP system) must have the same line size. I
understand that it is more efficient, especially for the coherence
protocol. However, I think it is reasonable for different caches to
have different line sizes. I assume there is no data sharing between
workloads for now hence there is no cache coherence issue (although I
think a little bit redesign of the coherence protocol would make it
work).
I'm interested in modifying M5 to support different line sizes in L1s
and the shared L2 (while L2's line size is always larger than all
L1's). Would anybody give me any suggestion?
1) I think modifying the addressing and cache line filling during a L1
miss is all I have to do, right? Any advice on where I should be
looking at?
2) For not messing up with coherence protocol, I may need to disable
it. Any advice on where I should be looking at (like, stop each core
from snooping the bus)? Will there be any side-effect if I do this?
Thanks.
--
Best Regards,
Wang, Weixun
Department of Computer& Information Science& Engineering
Gator College of Engineering
University of Florida
Gainesville, FL 32611
http://www.cise.ufl.edu/~wewang
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