Weixun Wang wrote: > Hi all, > > I'm trying to get M5 work with different line sizes in different > caches (i-cache, d-cache and l2). I found that M5 works fine with a > lot of scenarios where different caches have different line sizes > among cores (I verified the simulated apps' outputs). However, when it > comes to some other cases, especially when the L2 cache size is small > (e.g. 32kB), I got errors "Tried to access/execute unmapped address > XXX" from ItbPageFault::invoke() and NDtbMissFault::invoke(). > > I made M5 dump out messages throughout the memory access process > during simulation. I found that the error is caused by an invalid > virtual address of PC or data address. For example, in the read() > function of TimingSimpleCPU, (system.cpu TimingSimpleCPU::read() addr > = 7776240), the passed in parameter addr (which is the virtual > address) got the value "7776240", which is obviously an invalid > virtual address since in that case normal load/store has the vaddr of > sth like "4832631768". Therefore, the next step, which is calling the > TLB to translate the address, report such an error after looking up > the page table. > > There is no error if the line sizes are the same. So I suppose the > error comes from line size differences. But I went through the M5 > source code and found that actually memory access has taken the line > size differences among cache levels into consideration by > differentiating "size" stored in Request/Packet and the block size in > each cache. Block filling functions are also written in a right > manner. Moreover, the error comes from a bad virtual address in the > first place, which indeed has nothing to do with cache accesses. I'm > confused... > > Any help will be appreciated! > > Thanks! >
Using different line sizes isn't supported, and it isn't surprising it doesn't entirely work. It's likely the different sizes corrupted the virtual address as it was brought in from memory, or corrupted a value used to compute it. This segfault in the simulated program is probably a symptom of a problem that happened earlier. Gabe _______________________________________________ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
