That would probably work. Thanks for cluing me in... hadn't thought about verification applications.
Steve On Wed, Jul 21, 2010 at 12:48 PM, Eberle <rambo.u...@gmail.com> wrote: > What about using only an icache and no dcache? > We're experimenting with a new verification technique and want to observe > the behavior with and without caches. > > -- > Eberle. > > > On Wed, Jul 21, 2010 at 2:37 PM, Steve Reinhardt <ste...@gmail.com> wrote: >> >> O3 can deadlock if it doesn't have independent I&D caches... if the >> dcache blocks, the pipeline will continuously replay blocked loads, >> which saturates the icache port and will prevent the blocked loads >> from issuing if they don't have an independent path. >> >> (At least that's how I remember it... I'm not sure why we go all the >> way back to fetch to replay the blocked loads, but it's something like >> that.) >> >> We never bothered to deal with it because we couldn't think of a >> reasonable scenario where anyone would want a detailed CPU model w/o a >> reasonably detailed cache hierarchy too. I'm curious what your >> motivation is... >> >> Steve >> >> On Wed, Jul 21, 2010 at 10:06 AM, Eberle <rambo.u...@gmail.com> wrote: >> > Is there a way to use the O3 CPU without caches, only using the main >> > memory? >> > >> > Thanks, >> > >> > -- >> > Eberle. >> > >> > _______________________________________________ >> > m5-users mailing list >> > m5-users@m5sim.org >> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > >> _______________________________________________ >> m5-users mailing list >> m5-users@m5sim.org >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > _______________________________________________ > m5-users mailing list > m5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
