My mistake, it looks like the CWP is set as serializing... Thus, no way to increase IPC on a sparc?
On Thu, Aug 26, 2010 at 2:48 AM, john <[email protected]> wrote: > Hello, > > I have been simulating the MiBench suite using SPARC and noticed a very > strange behaviour (changeset used 7514:b28e7286990c). Even in the default > configuration of m5 (which is 8-wide) I couldn't get proper IPC rates. > > e.g. running mibench/automotive/basicmath_small for ~1/3 of the total > instructions: > .. > System.switch_cpus.ipc_total 0.336181 > # IPC: Total IPC of All Threads > .. > System.switch_cpus.committedInsts_total 50000001 > # Number of Instructions Simulated > .. > System.switch_cpus.numCycles 148729557 > # number of cpu cycles simulated > .. > System.switch_cpus.rename.RENAME:serializeStallCycles 59054076 > # count of cycles rename stalled for serializing inst > System.switch_cpus.rename.RENAME:serializingInsts 6605490 > # count of serializing insts renamed > > Now this means that 40% of the cycles are due to serializing instructions. > Some more inspection (if I'm correct) shows that decoder.isa declares > only tcci, tccx as serialized instructions. Single stepping in gdb shows > that the "save" instruction / mnemonic is serialized. Indeed, in the > generated build/SPARC_SE/arch/sparc/decoder.cc file (line ~7527): > inline Save::Save(ExtMachInst machInst) > : IntOp("save", machInst, IntAluOp) > { > > .... > flags[IsInteger] = true; > flags[IsNonSpeculative] = true; > flags[IsSerializeAfter] = true; > flags[IsSerializing] = true;; > } > > The question is, is "save" supposed to be serialized? If so, I must find > another reason why my IPC rates are so low, otherwise this looks like a bug > on the generation of the decoder.cc file. > > Thanks in advance, > John > >
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