Hello All,
If i try using cache block size of 4 for dcache, it'll give me an error. [command] build/SPARC_SE/m5.debug config/example/se.py -d --cache -c $benchmark -o $input [error message] m5.debug: build/SPARC_SE/mem/cache/cache_impl.hh:165 void Cache<TagStore>::satisfyCpuSideRequest(Packet*, typename TagStre::BlkType*) [with TagStore = LRU]: Assertion `pkt->getOffset(blkSize) + pkt->getSize() <= blkSize' failed. It seems like the problem only affects the dcache. icache block size = 4, dcache block size = 4 -> error icache block size = 4, dcache block size = 8 -> no error icache block size = 8, dcache block size = 8 -> no error >From my understanding, pkt->getOffset(blkSize) checks if the address is correct pkt->getSize() <= blkSize checks if the size is correct I've been trying to debug this with gdb and it seems like both getOffset and getSize assertions are failing. Regarding this I have two questions as well: 1. Is it because it's a 64bits and 4 bytes cannot be accessed? 2. icache is working with 4 bytes because 32bit instructions are processed? Could someone help me figure out a way to solve this problem? Thank you! -Glenn _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
