Hi Lide,
Thank you for your quick response. Actually when I used the patched splash
from udel website it works correctly but I thought only one thread is
running because the output stats doesn't show the stats for each thread
separately. Now I am trying to use atomic cpu for booting and then switch to
detailed cpu but I don't know how I tried to use: (-s option) but i got an
error
command line: ./build/ALPHA_FS/m5.opt ./configs/example/fs.py -n 4
--standard-switch --cache -b OCEAN
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/ziad-local/research/m5/src/python/m5/main.py", line 359, in
main
exec filecode in scope
File "./configs/example/fs.py", line 197, in <module>
Simulation.run(options, root, test_sys, FutureClass)
File "/home/ziad-local/research/m5/configs/common/Simulation.py", line
169, in run
testsys.switch_cpus = switch_cpus
File "/home/ziad-local/research/m5/src/python/m5/SimObject.py", line 621,
in __setattr__
self.add_child(attr, value)
File "/home/ziad-local/research/m5/src/python/m5/SimObject.py", line 667,
in add_child
(name, child._name, child._parent)
AttributeError: 'SimObjectVector' object has no attribute '_name'
or switching should be done in rcS file. I don't know
Can you please tell me how to do that?
thanks.
Ziad.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
On Fri, Oct 29, 2010 at 1:21 PM, Lide Duan <[email protected]> wrote:
> I am using the patched splash2 version from udel website, and it works
> fine. You need to follow the instructions on the link you mentioned to
> compile splash2. If you are using the pre-built disk image from M5 website,
> you need to use this cross-compiler:
> http://www.m5sim.org/dist/current/alpha_crosstool.tar.bz2
>
> Since you have only 1 CPU, the M5 stats output will show only 1 cpu. The
> number of threads won't show in the output. The context switching only
> happens in the OS.
>
> Besides, I would suggest to use atomic CPU to boot up the Linux first and
> then switch to detailed model for measurement. Otherwise, it will take a
> long time (several hours) to simply boot the OS.
>
> Lide
>
> On Fri, Oct 29, 2010 at 11:44 AM, ziad abuowaimer <
> [email protected]> wrote:
>
>> Hi All,
>>
>> I am trying to run splash2 on FS mode for alpha linux. I downloaded the
>> splash source file and recompile it using alpha-linux cross-compiler from m5
>> website. I followed the procedure described in
>> http://www.capsl.udel.edu/splash/Download.html
>> I used : c.m4.null.POSIX_BARRIER Macro to compile for PARMACS as
>> suggested.
>> also used these libraries for linking: libpthread.so.0 libc.so.6.1
>> ld-linux.so.2
>> then make ocean benchmark and got the executable file OCEAN correctly.
>> I run the OCEAN on FS mode using fs.py for one cpu and numThreads = 1 it
>> works fine
>> but when I tried to run it on one cpu with multithreading (numThreads=4)
>> it seems that it run only one thread ( note I ran OCEAN -p4).
>> ./build/ALPHA_FS/m5.opt ./config/examples/fs.py -d --cache -b OCEAN
>>
>> Later I use different macro pthread.m4.stougie found it in
>> http://kbarr.net/splash2.html
>> got the executable file OCEAN run fs.py as above with one cpu and 4
>> threads it shows in the system.terminal thread 1 created
>> and it works forever and after 1 day I killed the process and found in
>> stats.txt :
>> this is part of stats.txt:
>> system.cpu.iew.lsq.thread.0.blockedLoads
>> 0 # Number of blocked loads due to partial load-store
>> forwarding
>> system.cpu.iew.lsq.thread.0.cacheBlocked
>> 13560 # Number of times an access to memory failed due
>> to the cache being blocked
>> system.cpu.iew.lsq.thread.0.forwLoads
>> 440586 # Number of loads that had data forwarded from
>> stores
>> system.cpu.iew.lsq.thread.0.ignoredResponses
>> 373 # Number of memory responses ignored because the
>> instruction is squashed
>> system.cpu.iew.lsq.thread.0.invAddrLoads
>> 0 # Number of loads ignored due to an invalid address
>> system.cpu.iew.lsq.thread.0.invAddrSwpfs
>> 0 # Number of software prefetches ignored due to an
>> invalid address
>> system.cpu.iew.lsq.thread.0.memOrderViolation
>> 2307678 # Number of memory ordering violations
>> system.cpu.iew.lsq.thread.0.rescheduledLoads
>> 5766 # Number of loads that were rescheduled
>> system.cpu.iew.lsq.thread.0.squashedLoads
>> 38779193 # Number of loads squashed
>> system.cpu.iew.lsq.thread.0.squashedStores
>> 8228342 # Number of stores squashed
>> system.cpu.iew.memOrderViolationEvents
>> 2307678 # Number of memory order violations
>> system.cpu.iew.predictedNotTakenIncorrect
>> 444007 # Number of branches that were predicted not
>> taken incorrectly
>> system.cpu.iew.predictedTakenIncorrect
>> 1003438 # Number of branches that were predicted taken
>> incorrectly
>> system.cpu.ipc
>> 0.564378 # IPC: Instructions Per Cycle
>> system.cpu.ipc_total
>> 0.564378 # IPC: Total IPC of All Threads
>>
>>
>> does this means only one thread is executing and why it works forever and
>> not switching b/w threads? Is that macro that I am using is correct?
>> I appreciate your help.
>>
>> thanks.
>>
>> Ziad.
>>
>>
>>
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>
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