my command line is : %build/ALPHA_FS/m5.opt -d /tmp/output configs/examples/fs.py -n 2 -b fft
I haven't made any changes to m5. i am just running a test simulation before i apply changes to m5. I also tried to telnet into the simulation and it indicated there was no simulation happening. Here is my Stats.txt ---------- Begin Simulation Statistics ---------- host_mem_usage 109080 # Number of bytes of host memory used host_seconds 218.19 # Real time elapsed on the host host_tick_rate 289077337 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.063073 # Number of seconds simulated sim_ticks 63072794750 # Number of ticks simulated system.cpu0.dtb.data_accesses 0 # DTB accesses system.cpu0.dtb.data_acv 0 # DTB access violations system.cpu0.dtb.data_hits 0 # DTB hits system.cpu0.dtb.data_misses 0 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 0 # DTB read accesses system.cpu0.dtb.read_acv 0 # DTB read access violations system.cpu0.dtb.read_hits 0 # DTB read hits system.cpu0.dtb.read_misses 0 # DTB read misses system.cpu0.dtb.write_accesses 0 # DTB write accesses system.cpu0.dtb.write_acv 0 # DTB write access violations system.cpu0.dtb.write_hits 0 # DTB write hits system.cpu0.dtb.write_misses 0 # DTB write misses system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.fetch_accesses 252291180 # ITB accesses system.cpu0.itb.fetch_acv 0 # ITB acv system.cpu0.itb.fetch_hits 252291180 # ITB hits system.cpu0.itb.fetch_misses 0 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.write_acv 0 # DTB write access violations system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu0.kern.mode_good::kernel 0 system.cpu0.kern.mode_good::user 0 system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu0.kern.mode_switch::user 0 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good::kernel no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu0.kern.swap_context 0 # number of times the context was actually changed system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.numCycles 252291180 # number of cpu cycles simulated system.cpu0.num_insts 0 # Number of instructions executed system.cpu0.num_refs 0 # Number of memory references system.cpu1.dtb.data_accesses 0 # DTB accesses system.cpu1.dtb.data_acv 0 # DTB access violations system.cpu1.dtb.data_hits 0 # DTB hits system.cpu1.dtb.data_misses 0 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 0 # DTB read accesses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_hits 0 # DTB read hits system.cpu1.dtb.read_misses 0 # DTB read misses system.cpu1.dtb.write_accesses 0 # DTB write accesses system.cpu1.dtb.write_acv 0 # DTB write access violations system.cpu1.dtb.write_hits 0 # DTB write hits system.cpu1.dtb.write_misses 0 # DTB write misses system.cpu1.idle_fraction 0 # Percentage of idle cycles system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.fetch_accesses 252291180 # ITB accesses system.cpu1.itb.fetch_acv 0 # ITB acv system.cpu1.itb.fetch_hits 252291180 # ITB hits system.cpu1.itb.fetch_misses 0 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.write_acv 0 # DTB write access violations system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.mode_good::kernel 0 system.cpu1.kern.mode_good::user 0 system.cpu1.kern.mode_good::idle 0 system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches system.cpu1.kern.mode_switch::user 0 # number of protection mode switches system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches system.cpu1.kern.mode_switch_good::kernel no_value # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user no_value # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total no_value # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.numCycles 252291180 # number of cpu cycles simulated system.cpu1.num_insts 0 # Number of instructions executed system.cpu1.num_refs 0 # Number of memory references system.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. system.disk0.dma_write_txs 0 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. system.disk2.dma_write_txs 0 # Number of DMA write transactions. system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR ---------- End Simulation Statistics ---------- _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
