Hi all,
A simple question. Could any one tell me that is the miss latency (e.g.,
system.cpu.dcache.overall_miss_latency) in M5 simulation output file? It
is apparently not "# number of overall miss cycles" since it has a very
huge value (e.g., 751856570000 while the cpu cycles simulated is only
783263851). Moreover, how is this latency calculated?
And I'm assuming all cache access latency, miss latency, block fill time
are incorporated in "system.cpu.numCycles", right?
Thanks.
--
Best Regards,
Wang, Weixun
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