We are trying to create private L2 caches for each cpu. The following code
was added/changed in run.py and tried executing with FMM benchmark.


 #here l2 private cache for each cpu  is named as s_r_cache

s_r_caches=[BaseCache(size = options.l2size,
           assoc = 8)
        for i in xrange(options.numcpus)]

# ----------------------
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cpus, physmem = PhysicalMemory(),s_r_cache=s_r_caches,
                membus = Bus(clock = busFrequency))



for i in xrange(options.numcpus):
    system.s_r_cache[i].bus=Bus(clock = busFrequency)
    system.s_r_cache[i].cpu_side = system.s_r_cache[i].bus.port    # Each
private s_r_cache (l2 cache)  is connected to each cpu
    system.s_r_cache[i].mem_side = system.membus.port



# ----------------------
# Connect the L2 cache and memory together
# ----------------------

system.physmem.port = system.membus.port

# ----------------------
# Connect the L2 cache and clusters together
# ----------------------
for cpu in cpus:
    cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
                                L1(size = options.l1size, assoc = 4))

    cpu.connectMemPorts(system.s_r_cache[i].bus)


We faced the following errors :


M5 Simulator System

Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved


M5 compiled Oct 16 2010 01:36:31
M5 revision Unknown
M5 started Nov  4 2010 02:01:25
M5 executing on sunita
command line: build/ALPHA_SE/m5.debug configs/splash2/run.py --rootdir
splash/splash2/codes -t --frequency 1GHz -n 4 --l1size 64kB --l2size 256kB
--l1latency 4ns --l2latency 11ns -b FMM
Global frequency set at 1000000000000 ticks per second
Error in unproxying param 'prefetch_latency' of system.s_r_cache0
Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/home/sunita/Desktop/m5/src/python/m5/main.py", line 359, in main
    else:
  File "configs/splash2/run.py", line 295, in <module>
    m5.instantiate()
  File "/home/sunita/Desktop/m5/src/python/m5/simulate.py", line 64, in
instantiate
    for obj in root.descendants(): obj.unproxyParams()
  File "/home/sunita/Desktop/m5/src/python/m5/SimObject.py", line 732, in
unproxyParams
    value = value.unproxy(self)
  File "/home/sunita/Desktop/m5/src/python/m5/proxy.py", line 94, in unproxy
    (self.path(), self._pdesc.ptype_str, base.path())
AttributeError: Can't resolve proxy 'latency' of type 'Latency' from
'system.s_r_cache0'




-- 
Sunitha.P
9092892876
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