Thank you, Ali. It seems that this is the reason, because I always found that the two instruction when they are memory instructions (I am only interested in this type) have exactly the same access address. I think I need to consider this issue in my statistics. Thanks.
On Sun, Nov 14, 2010 at 8:15 PM, Ali Saidi <[email protected]> wrote: > You would have to provide us with at Exec trace of it happening to be sure, > but the only reason that comes to mind is if the instruction takes a fault > or is a syscall, the atomic cpu might execute the faulting instruction and > the first instruction of the fault handler in the same cycle. > > Ali > > On Nov 14, 2010, at 12:24 AM, Veydan Wu wrote: > > > Hi, I am using the atomic CPU in alpha FS mode. Because I need to do some > statistics based on instruction count, two instructions in the same "tick" > makes some instruction count be 0. Could someone tell me why it occurs given > that the "width" parameter is "1" by default? thanks. > > > > -- > > weidan > > _______________________________________________ > > m5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- Regards, Weidan Wu
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