On Fri, 17 Dec 2010, Matthew Horsnell wrote:
> Is anyone in the m5 community aware of any empirical studies of M5 accuracy, > at various levels: e.g. branch prediction, cache misses, IPC, executed > instructions etc; for any standard benchmark suites? You can take a look at my thesis: http://www.csl.cornell.edu/~vince/thesis/index.html Appendix C.10 has a comparison of x86_64 retired instruction m5 results compared to HW perf counter (pentium D) and Valgrind. It usually matches within 1%, but m5 is not as close to actual hardware as Valgrind is. Appendix C.1 has a comparison of Alpha retired instruction m5 results compared to Qemu results (they match closely). I unfortunately no longer have access to my Alpha machine, which is sad because as of 2.6.35 Linux now has perf_events support and I could have gotten real results to compare against. In general most simulators match OK with deterministic events, such as retired instructions. (Though you have to be careful, see a recent presentation I made at the FHPM workship about the accuracy of retired instruction hw counters on recent machines: http://web.eecs.utk.edu/~vweaver1/projects/deterministic/ ) For other metrics, you can get somewhat OK matches with real hardware on simpler older cores, such as MIPS cpus. All bets are off on modern OoO chips that do things like advanced prefetching and branch predicting. Especially once multi-core gets involved. You can see my aforementioned PhD thesis for more info on this than you probably care to read. Vince _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
