Ali is correct, there were plans to have the inorder model support ARM but were shelved until the O3 support was more mature.
Now that O3-ARM is in a much better state, I do plan on bringing up initial ARM support for inorder in the next few months (i.e. our basic regression tests in the m5-dev tree). On Tue, Dec 21, 2010 at 5:50 PM, Ali Saidi <[email protected]> wrote: > Hi Marc, > > No one has started to work on the ARM in-order model. Korey Sewell was > contemplating working on it, but I don't know if he has actually started. > > Thanks, > Ali > > > > On Dec 21, 2010, at 4:59 PM, Marc de Kruijf wrote: > > Dear M5, > > I have been poking around M5 to a greater depth than before and I have a > few questions. > > 1. Regarding x86, it seems that neither the in-order or out-of-order > models are yet supported. What is the status of these efforts? What work > needs to be done for these models (particularly o-o-o) to become usable. I > am not particularly interested in full-system support, so the question is > mostly with respect to system-call emulation. > > 2. Regarding ARM, the out-of-order model appears to be pretty far along. > That's great! However, there is currently no in-order model support. Is > there work ongoing regarding this? How far along is it? Again, what work > needs to be done? > > Lastly, when I run the se.py example config in the X86 SE configuration I > get an assertion failure. Here is the console output: > > $ build/X86_SE/m5.debug configs/example/se.py > M5 Simulator System > > Copyright (c) 2001-2008 > The Regents of The University of Michigan > All Rights Reserved > > M5 compiled Dec 20 2010 16:06:23 > M5 revision 85e1847726e3 7798 default tip > M5 started Dec 21 2010 15:42:52 > M5 executing on venus.cs.wisc.edu > command line: build/X86_SE/m5.debug configs/example/se.py > Global frequency set at 1000000000000 ticks per second > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > m5.debug: build/X86_SE/arch/x86/insts/macroop.hh:79: virtual StaticInstPtr > X86ISA::MacroopBase::fetchMicroop(MicroPC) const: Assertion `microPC < > numMicroops' failed. > Program aborted at cycle 500 > Aborted > > Is this a known problem? Am I doing something wrong? ARM and ALPHA both > seem to be okay. > > Marc > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- - Korey
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