[m5-users] the dataflow from processor to cache

Wed, 02 Feb 2011 09:28:41 -0800 

Hi all, plz correct me if i am wrong regarding to this flow:

CPU---------->L 1
CACHE-----HIT------>RETURN<------------------------------------------------------------------------
                        |                                ^

|
                        |
|
|
                        |
|
|
                       MISS
HIT
|
                        |
|
HIT
                        |
|
|
                        -------------------->PREFETCHER (PREFETCH
QUEUE)-----------MISS-------------> MSHRs---------MISS---------> L2 CACHE
....................... and so on
ASSUMING CACHE IS WARM AT  THIS STAGE.







-- 

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*
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