yeah u can implement of your own like this:
class L3(BaseCache):
size = "8MB"
block_size = 64
latency = "24ns"
mshrs = 8
tgts_per_mshr = 4
write_buffers = 8
assoc = 16
and use this function:. addTwoLevelCacheHierarchy and add cpuside ports and
memory side ports for l3 cache
On Fri, Feb 4, 2011 at 9:55 PM, Sheng Li <[email protected]> wrote:
> Hi Guys,
>
> I am a newbie to M5. When running M5, I coded some python scripts and used
> the default python files in ./config/ as the base. However, I realized that
> some options in the Option.py were not implemented. For example, the l3cache
> related options are in the Option.py file but not implemented anywhere. Did
> I miss something? I can implement those are missing and just want to make
> sure I am not missing some thing obvious.
>
> Thanks!
> -Sheng Li
>
>
>
> _______________________________________________
> m5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>
--
*thanks®ards
*
*BISWABANDAN PANDA*
*M.S.(RESEARCH SCHOLAR)*
*RISE LAB*
*IIT MADRAS*
http://www.cse.iitm.ac.in/~biswa/ <http://www.cse.iitm.ac.in/%7Ebiswa/>
_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users