The cache itself does not have a clock; it is driven by requests that come in from the CPU-side bus, so basically if you want to change the throughput of a cache you do that by changing the clock of its CPU-side bus.
Steve On Sat, Feb 5, 2011 at 8:39 AM, Sheng Li <[email protected]> wrote: > Thanks Nate! > > Should i set different clock rates in the bus() to have multiple clock > domains? We cannot set clock in cache object. > > Thanks > -Sheng > > > On Sat, Feb 5, 2011 at 10:35 AM, nathan binkert <[email protected]> wrote: > >> > When report stats, M5 uses cycle as units. It seems to me the reported >> > "cycle" is the real cycle determined by the core clock rate, not the >> > internal tick, right? What should I do if I need to model a processor >> with >> > different clock domains? For example, the core is running at 2Ghz, >> while >> > the L3 is running at 500 Mhz. It seems we cannot set the clock of >> different >> > components. Did I missed something? >> >> When things are reported per cycle, we generally divide by the clock >> period. If you're doing multiple and/or changing clock domains, I'd >> suggest reporting latencies in nanoseconds. >> >> Nate >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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