Without actually looking at the code, I'm pretty sure those flags just
aren't being set when those instructions are defined. That would be
done in the ISA description files in the arch/arm/isa directory. I
don't think instructions that set R15 (the PC register) are currently
being marked as control instructions. Also whether an instruction is
conditional or not is a fuzzy concept in ARM. They can all be
conditional because of predicated execution, with a few exceptions,
but often the condition is "always" which is effectively
unconditional. The current ARM maintainers (Ali and others) might be
better able to help you. I might implement something too, but I can't
test changes as well as they can and might not have time for a while.
Gabe
Quoting Andrew Lukefahr <[email protected]>:
Hi,
I'm trying to determine when a StaticInst is a conditional vs unconditional
branch using the ARM ISA. The StaticInstBase class has a isControl()
function that seems to work, but the isCondCtrl() and isUncondCtrl() do
not. Further grep'ing revealed that in my build/ARM_SE/arch/arm/decoder.cc
file, I have lots of "flags[IsControl]=true;" statements, but none for the
CondCtrl and UncondCtrl.
So,
1) Is there a better way to decide if an inst is a conditional vs
unconditional branch?
2) If not, where would I add cond/uncond flags to the ISA?
Thanks
Andrew Lukefahr
[email protected]
Open Source, Open Minds
_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
