Hi all, I analyzed cache_imple.hh and got the understanding that
when a miss occurs in L1 , it is searched in MSHR queue, if miss in MSHR also, L2 is searched. But I want some information to be passed directly from L1 to L2 without processing MSHR. Is it possible...?...Can i implement here....? kindly help -- Sunitha.P 9092892876
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