i think it will work, just check it and get back to me On Thu, Feb 17, 2011 at 8:35 AM, Adwait Jog <[email protected]> wrote:
> I want the read and write latencies for caches to be different. Is it ok, > to change the latency numbers in cache_impl.hh when there is a write (by > checking pkt->isWrite()), or do I need to take care of something else? > > ---- Adwait > > > >> > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- *thanks®ards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/
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